Digital prototype of LLRF system for SSRF

This paper describes a field programming gate array (FPGA) based low level radio frequency (LLRF) prototype for the SSRF storage ring RF system. This prototype includes the local oscillator (LO), analog front end, digital front end, RF out, clock distributing, digital signal processing and communication functions. All feedback algorithms are performed in FPGA. The long term of the test prototype with high power shows that the variations of the RF amplitude and the phase in the accelerating cavity are less than 1% and 1° respectively, and the variation of the cavity resonance frequency is controlled within ±10 Hz.