A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation

被引:2
作者
郑永正
李伟男
夏玲琍
黄煜梅
洪志良
机构
[1] StateKeyLaboratoryofASIC&SystemFudanUniversity
关键词
phase-locked loop; adaptive frequency calibration; loop filter; CMOS; UWB;
D O I
暂无
中图分类号
TN914.41 [跳频通信];
学科分类号
0810 ; 081001 ;
摘要
A fully integrated phase-locked loop(PLL) is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.
引用
收藏
页码:89 / 93
页数:5
相关论文
共 1 条
[1]  
A 4-GHz clock system for ahigh-performance system-on-chip design .2 Ingino J M,Kaenel V R. IEEE JSol Sta Circ . 2001