Design of high performance and radiation hardened SPARC-V8 processor

被引：0

作者：

赵元富 ^{[1
]}

覃辉 ^{[1
]}

彭和平 ^{[1
]}

于立新 ^{[1
]}

机构：

[1] Beijing Microelectronics Technology Institute

来源：

Journal of Semiconductors | 2015年 / 11期

关键词：

processor; radiation hardening; fault-tolerant architecture; radiation effects;

D O I：

暂无

中图分类号：

TP332 [运算器和控制器（CPU）];

学科分类号：

081201 ;

摘要：

Design of a highly reliable SPARC-V8 processor for space applications requires consideration singleevent effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose(TID). In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78 9.78 mm2, and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements’ experiments, which show TID resistance to 300 krad(Si), SEL immunity to greater than 92.5 Me V cm2/mg, and an SEU error rate of 2.51 10-4per day.

引用

页码：93 / 95

页数：3