A High-Speed Dual Modulus Prescaler Using 0.25 μm CMOS Technology

被引：0

作者：

杨文荣

曹家麟

冉峰

王健

机构：

[1] MicroelectronicResearchandDevelopmentCenter,ShanghaiUniversity,Shanghai,PRChina,MicroelectronicResearchandDevelopmentCenter,ShanghaiUniversity,Shanghai,PRChina,MicroelectronicResearchandDevelopmentCenter,ShanghaiUniversity,Shanghai,PRChina,MicroelectronicR

来源：

Journal of Shanghai University | 2004年 / 03期

关键词：

CMOS; prescaler; source-coupled logic(SCL); phase-locked loop(PLL);

D O I：

暂无

中图分类号：

TN432 [场效应型];

学科分类号：

080903 ; 1401 ;

摘要：

A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.

引用

页码：342 / 347

页数：6