A novel digital etch technique for deeply scaled III-V MOSFETs

被引：40

作者：

Lin, Jianqiang ^{[1
]}

Zhao, Xin ^{[1
]}

Antoniadis, Dimitri A. ^{[1
]}

Del Alamo, Jesus A. ^{[1
]}

机构：

[1] Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge

来源：

IEEE Electron Device Letters | 2014年 / 35卷 / 04期

基金：

美国国家科学基金会;

关键词：

buried-channel; Digital etch; InGaAs; MOSFETs; quantum-well devices; Self-alignment;

D O I：

10.1109/LED.2014.2305668

中图分类号：

学科分类号：

摘要：

We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of low-power O2 plasma oxidation, followed by diluted H2SO4 rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ∼0.9 nm/cycle. We illustrate the new process by fabricating Lg = 60-nm self-aligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO 2 for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/μm (Vds = 0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at Vds = 0.05 and 0.5 V, respectively, and on current of 326 μA/μm at IOFF =100 nA/μm and Vdd = 0.5 V. © 1980-2012 IEEE.

引用

页码：440 / 442

页数：2

共 14 条

[1]

Del Alamo J.A., Antoniadis D., Guo A., Et al., InGaAs MOSFETs for CMOS: Recent advances in process technology, IEDM Tech. Dig., pp. 24-27, (2013)

[2]

Radosavljevic M., Chu-Kung B., Corcoran S., Et al., Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications, Proc. IEEE IEDM, pp. 319-322, (2009)

[3]

Radosavljevic M., Dewey G., Fastenau J.M., Et al., Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications, Proc. IEEE IEDM, pp. 126-129, (2010)

[4]

Terao R., Kanazawa T., Ikeda S., Et al., InP/InGaAs composite metaloxide-semiconductor field-effect transistors with regrown source and Al2O3 gate dielectric exhibiting maximum drain current exceeding 1.3 mA/?m, Appl. Phys. Exp., 4, 5, pp. 0542011-0542013, (2011)

[5]

Kim D.-H., Hundal P., Papavasiliou A., Et al., E-mode planar Lg = 35 nm In0.7Ga0.3As MOSFETs with InP/Al2O3/HfO2 (EOT = 0.8 nm) composite insulator, Proc. IEEE IEDM, pp. 761-764, (2012)

[6]

Lin J., Antoniadis D.A., Del Alamo J.A., Sub-30 nm InAs quantum-well MOSFETs with self-aligned metal contacts and Sub-1 nm EOT HfO2 insulator, Proc. IEEE IEDM, pp. 757-760, (2012)

[7]

Athavalea S.D., Economoub D.J., Realization of atomic layer etching of silicon, J. Vac. Sci., Technol. B, 14, 6, pp. 3702-3805, (1996)

[8]

Ko K.K., Pang S.W., Controllable layer-by-layer etching of III-V compound semiconductors with an electron cyclotron resonance source, J. Vac. Sci. Technol. B, Vol., 11, 6, pp. 2275-2279, (1993)

[9]

DeSalvo G.C., Bozada C.A., Ebel J.L., Look D.C., Barrette J.P., Cerny C.L.A., Dettmer R.W., Gillespie J.K., Havasy C.K., Jenkins T.J., Nakano K., Pettiford C.I., Quach T.K., Sewell J.S., Via G.D., Wet chemical digital etching of GaAs at room temperature, Journal of the Electrochemical Society, 143, 11, pp. 3652-3656, (1996)

[10]

Alian A., Merckling C., Brammertz G., Et al., InGaAs MOS transistors fabricated through a digital-etch gate-recess process and the influence of forming gas anneal on their electrical behavior, ECS J. Solid State Sci. Technol., 1, 6, pp. 310-314, (2012)

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