A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA

被引:0
作者
Krishnan, Abi K. [1 ]
Supriya, M. H. [1 ]
Nalesh, S. [1 ]
机构
[1] Cochin Univ Sci & Technol, Dept Elect, Kochi, Kerala, India
来源
2021 25TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST, VDAT | 2021年
关键词
Data acquisition system; Hardware-Software co-design; Distributed System Synchronization; IEEE; 1588; PTP;
D O I
10.1109/VDAT53777.2021.9600989
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Data acquisition systems are required to condition the low-level analog signals from various sensors and to convert them into digital format in order to facilitate downstream processing. Distributed DAQ systems are commonly used in SONAR systems, as a large number of acoustic sensors are used in big platforms and the sensors are physically distributed. The data collected by the distributed DAQ systems are transmitted to a central processing system in real-time where further processing of the data is done. The operating environment of the underwater system can impose severe restrictions on the design of the DAQ system. This paper presents a hardware-software co-design based approach to implementing a resource-efficient FPGA-based distributed DAQ system. Here, the functionality of deterministic data transmission through Ethernet is implemented using RTL modules, and remote health monitoring and configuration control functionalities with TCP/IP stack support are implemented in a soft-processor inside FPGA. To reduce the number of external cables and the FPGA resource utilization, a single Ethernet MAC is shared between processor and RTL modules using AXI switches. Synchronized sampling of sensors is an important requirement in distributed DAQ systems. In this paper, synchronization is achieved by implementing the IEEE1588 precision time protocol in FPGA. By implementing the timestamping of the PTP messages at the RGMII interface, synchronization accuracy close to 300ns was achieved. The implementation was done on Artix7 FPGA from Xilinx with a resource utilization of 36K LUTs and 43K flip-flops. MicroBlaze soft-processor was used with 100 MHz clock and the Synchronization Timer was generated using a 200 MHz clock.
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页数:6
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