Enhancing FPGA Routing Efficiency with Graph Neural Network-Based Congestion Prediction

被引：0

作者：

Tokuishi, Kazuki ^{[1
]}

Amagasaki, Motoki ^{[2
]}

Kiyama, Masato ^{[2
]}

Seto, Kenshu ^{[3
]}

机构：

[1] Kumamoto Univ, Grad Sch Sci & Technol, Kumamoto, Japan

[2] Kumamoto Univ, Fac Adv Sci & Technol, Kumamoto, Japan

[3] Kumamoto Univ, Res & Educ Inst Semicond & Informat REISI, Kumamoto, Japan

来源：

PROCEEDINGS OF THE 15TH INTERNATIONAL SYMPOSIUM ON HIGHLY EFFICIENT ACCELERATORS AND RECONFIGURABLE TECHNOLOGIES, HEART 2025 | 2025年

关键词：

FPGA Routing; Congestion Prediction; Graph Neural Network;

D O I：

10.1145/3728179.3728185

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In the design flow of field-programmable gate arrays, routing is highly time consuming and can take several hours or even days to complete for large-scale designs. This is due to resource contention during routing, which necessitates numerous iterative processes to identify the optimal routing pattern. Therefore, proposed here is a method in which a graph neural network is used to predict routing resource congestion and reduce routing time. Also, graph extraction tailored to the design size is performed to reduce the computational cost during congestion prediction. Evaluation results show that compared to Enhanced PathFinder, the proposed method reduces routing time by up to 75% while maintaining circuit performance.

引用

页码：131 / 137

页数：7

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