Heterogeneous Integration on Fan-Out Wafer Level Packaging Platform

被引：0

作者：

Chai, T. C. ^{[1
]}

Ho, David ^{[1
]}

Chong, S. C. ^{[1
]}

Lim, Sharon P. S. ^{[1
]}

Hsiao, H. Y. ^{[1
]}

Soh, Jacob ^{[1
]}

机构：

[1] ASTAR, Inst Microelect, 2 Fusionopolis Way,Innovis Tower, Singapore 138634, Singapore

来源：

2021 IEEE 23RD ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, EPTC | 2021年

关键词：

FOWLP;

D O I：

10.1109/EPTC53413.2021.9663922

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper provides an update on projects undertaken in the FOWLP development line namely the AiP in FOWLP for mmWave Radar Consortium and the newly launched Chiplet Consortium. Some of notable process development on RDL technologies being developed for heterogeneous integration high density chiplet packaging and multi-layer wafer level mold encapsulation capabilities will also be updated.

引用

页码：248 / 252

页数：5

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