Semiconductor Parametric Yield Prediction: A Combination of Machine Learning and Physics-Informed Approach

被引:0
作者
Sankaran, Karthik [1 ]
Mosleh, Ali [1 ]
Hakim, Kamran [2 ]
机构
[1] Univ Calif Los Angeles, B John Garrick Inst Risk Sci, 404 Westwood Plaza, Los Angeles, CA 90095 USA
[2] Teradyne Inc, 600 Riverpark Dr, North Reading, MA 01864 USA
来源
2025 ANNUAL RELIABILITY AND MAINTAINABILITY SYMPOSIUM, RAMS | 2025年
关键词
Machine Learning; ASICs; Semiconductor Yield; Process Nodes;
D O I
10.1109/RAMS48127.2025.10935067
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Semiconductor manufacturing is a multi-billion-dollar industry with yield being a fundamental factor in evaluating semiconductor device cost. The Yield is evaluated as the ratio of the number of working die over net number of die. Yield is regulated by different yield types: (1) Line Yield; (2) E-Test Yield; (3) Sort Yield; and (4) Final Test yield. Other than fab-related systematic factors affecting yield, E-test, sort & final test yield could either be defect-limited, or parametric-shift limited. The purpose of this work is to develop a model to estimate defect-limited and parametric-shift-limited yields which are primarily dealing with random yield. There are several proposed models in the public domain for defect-limited yield estimation. However, parametric shift is often estimated by simulation which is both time consuming and costly. Furthermore, simulation is not the method of choice for deciding which process to use for a particular design. A simpler approach is needed to determine if a process technology of choice provides adequate headroom, resulting in a reasonable yield for the design. The aim of this work is to model parametric-shift-limited yield using regression or deep machine learning (DML) techniques on final test data. This yield type is very sensitive to manufacturing process variation. Depending on the amount of headroom associated with an IC design, manufacturing fluctuation could influence the amount of shift on device parameters. While Semiconductor Foundries do not share many details regarding their processes since the data is proprietary, E-test (aka Wafer Acceptance Test or WAT) results for every manufacturing lot are available for evaluation. E-test summarizes the results of a series of simple test structures distributed on multiple locations on the wafer. These test structures provide a measure of basic device parameters such as V-th, I-Dsat and some others which represent a measure of variability in the manufacturing process. In this paper we present a model for estimating yield based on parametric shift. The involved datasets here will be E-test data and Final Test data. A Correlation analysis will be done between E-test data and Final test data using Machine Learning. Physics-informed models will then be used to estimate E-test parameters using process specific data. The resulting values will be used to estimate Final Test failure signatures using E-test correlation as a bridge between them. This process will involve both a data-based approach and a root cause yield prediction.
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