Design of High-speed Low-power Digital Interpolation Filters

被引:0
作者
Yao, Yafeng [1 ]
Wang, Tong [1 ]
Xu, Yangyang [1 ]
Xin, Zhengyu [2 ]
机构
[1] School of Mechanical Engineering and Electronic Information, China University of Geosciences(Wuhan), Wuhan
[2] Analog IC Key Laboratory, Chongqing Acoustic-Optic-Electronic Co. ,Ltd., Chongqing
来源
Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences | 2025年 / 52卷 / 06期
关键词
analog to digital converter; digital filters; digital up-conversion; field programmable gate arrays(FPGA); interpolation;
D O I
10.16339/j.cnki.hdxbzkb.2025189
中图分类号
学科分类号
摘要
In response to the issues of high hardware resource consumption and slow processing speed associated with traditional digital interpolation filters,a design methodology based on operand resource reuse is proposed to enhance digital interpolation filter performance. Building upon the foundation of a polyphase digital interpolation filter,this method optimizes the filter architecture to enable the reuse of core computational resources,resulting in a significant reduction in circuit resources and power consumption. A novel architecture filter proposed in this study is prototyped verified on an FPGA platform,and comparative analyses are conducted with traditional interpolation filters,multi-channel parallel interpolation filters,and polyphase interpolation filters. The results indicate that the improved filter requires 65% fewer registers compared to the traditional structure,73% fewer registers compared to the multi-channel parallel structure,and 28% fewer registers compared to the polyphase structure,respectively. The maximum operating clock frequency is increased by 129% compared to the traditional structure and 13.8% compared to the multi-channel parallel structure. Moreover,power consumption is lower than that of traditional structure and multi-channel paralle structure,making it more suitable for high-speed and low-power consumption applications. © 2025 Hunan University. All rights reserved.
引用
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页码:195 / 202
页数:7
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