Design of a Low-Cost Stochastic Computing-based Median Filter for Digital Image Processing

Stochastic computing (SC) is an approximate computation method that enables the design of low-cost and error-tolerant systems. The median filter (MF) is one of the widely used filters in image processing and is particularly effective in removing salt-and-pepper noise. In this paper, we propose an energy-efficient SC-based MF. The proposed SC-based MF increases hardware efficiency while maintaining performance quality by reducing the number of comparators. The proposed SC-based MF was implemented using Verilog HDL and synthesized using 65-nm CMOS technology. The proposed SC-based MF achieves up to 63.4% and 75.2% savings in area and power, respectively, compared to the binary implementation of MF. Furthermore, compared to the conventional SC-based MF, the proposed design improves by 13.2% and 10.2%, respectively. Despite a slight decrease in peak signal-to-noise ratio (PSNR), the proposed design exhibits excellent overall hardware performance.