Accelerating Inference on Binary Neural Networks with Digital RRAM Processing

被引:0
作者
Vieira, Joao [1 ]
Giacomin, Edouard [2 ]
Qureshi, Yasir [3 ]
Zapater, Marina [3 ]
Tang, Xifan [2 ]
Kvatinsky, Shahar [4 ]
Atienza, David [3 ]
Gaillardon, Pierre-Emmanuel [2 ]
机构
[1] Univ Lisbon, Inst Super Tecn, INESC ID, Lisbon, Portugal
[2] Univ Utah, LNIS, Salt Lake City, UT USA
[3] Swiss Fed Inst Technol Lausanne EPFL, ESL, Lausanne, Switzerland
[4] Technion Israel Inst Technol, Andrew & Erna Viterbi Fac Elect Engn, Haifa, Israel
来源
VLSI-SOC: NEW TECHNOLOGY ENABLER, VLSI-SOC 2019 | 2020年 / 586卷
基金
欧洲研究理事会;
关键词
Machine Learning; Embedded systems; Binary Neural Networks; RRAM-based Binary Dot Product Engine;
D O I
10.1007/978-3-030-53273-4_12
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The need for efficient Convolutional Neural Network (CNNs) targeting embedded systems led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the operands using only one bit. Also, due to 90% of the operations executed by CNNs and BNNs being convolutions, a quest for custom accelerators to optimize the convolution operation and reduce data movements has started, in which Resistive Random Access Memory (RRAM)-based accelerators have proven to be of interest. This work presents a custom Binary Dot Product Engine(BDPE) for BNNs that exploits the low-level compute capabilities enabled RRAMs. This new engine allows accelerating the execution of the inference phase of BNNs by locally storing the most used kernels and performing the binary convolutions using RRAM devices and optimized custom circuitry. Results show that the novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area.
引用
收藏
页码:257 / 278
页数:22
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