A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis

被引:0
作者
She, Yuhan [1 ]
Liu, Jierui [1 ]
Uang, Yanlong h [1 ]
Cheung, Ray c. c. [2 ]
Yan, Hong [2 ]
机构
[1] City Univ Hong Kong, Hong Kong, Peoples R China
[2] City Univ Hong Kong, Ctr Intelligent Multidimens Data Anal, Hong Kong, Peoples R China
关键词
high-level synthesis; speculative loop pipeline; pipelining; scheduling; FPGA; DATA-FLOW;
D O I
10.1145/3705732
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Loop pipelining is a key optimization in high-level synthesis (HLS), aimed at overlapping the execution of iterations. Static scheduling, dominant in commercial HLS tools, configures the pipeline based on compile-time analysis, proving conservative for designs with irregular control flow and memory access due to imbalanced recurrences. Speculative Loop pipeline (SLP) is a novel concept that addresses the problem by introducing the speculation and recovery mechanism at the source level to improve the throughput. Although proven promising, it has a significant gap from practical application: It requires accurate early-stage modeling of the pipeline configuration for each path, which is unable to obtain with classic HLS scheduling methods because the SLP process itself interferes with the path length. In this work, we made a step forward by proposing a practical SLP framework with accurate path modeling ability through iterative tuning. We further optimize the SLP technology by combining automatic dataflow extraction with speculative source-level transformation to further boost the performance in specific design patterns. Our framework works on the source level and is easy to be plugged into existing downstream HLS tools. Experiment results demonstrate significant performance improvements over commercial HLS tools and better resource trade-offs compared to the state-of-the-art dynamic-scheduling-based solutions.
引用
收藏
页数:33
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