Efficient Approximate Computing Circuits for Error-Tolerant Applications: Design and Validation of Multipliers with Novel Speculative Adders and Approximate Compressors

The development of energy-efficient circuits tailored for error-tolerant applications marks a significant advancement in low-power computing, particularly within the realm of approximate computing. This approach addresses the inherent trade-off between precise computation and computational efficiency. This study introduces a novel energy-efficient multiplier specifically designed for image-processing tasks. Integral to the multiplication process are compressors, which play a crucial role in reducing partial products. Moreover, higher-order approximate compressors, including 7:2 and 8:2 configurations, have been meticulously designed and simulated using Verilog coding within the VIVADO environment. The proposed approximated 7:2, and 8:2 compressors utilize 44%, and 41.37% less area, respectively, 52.35%, and 56.61% low-power consumption, respectively, and 13.73%, and 16.77% high speed, respectively, in comparison to exact compressors comparative analysis reveals that these proposed higher-order compressors offer reduced area requirements and lower power consumption compared to existing state-of-the-art techniques. Incorporating these high-performance compressors at the reduction stage of multipliers yields an energy-efficient circuit tailored for error-tolerant applications. The research employs three distinct designs (Design 1, Design 2 and Design 3), each leveraging the proposed higher-order compressors and approximate adders across varying bit-widths (8-, 16-, 32- and 64-bit). Each design presents unique advantages and limitations, catering to the specific requirements of the application.