Reset-dominant accurate synaptic weight mapping in passive memristor arrays for energy-efficient spiking neural networks

被引:0
作者
Byun, Yongjin [1 ]
Kim, Gimun [1 ]
Kim, Sungjoon [2 ]
Kim, Sungjun [1 ]
机构
[1] Dongguk Univ, Div Elect & Elect Engn, Seoul 04620, South Korea
[2] Korea Univ, Dept AI Semicond Engn, Sejong 30019, South Korea
基金
新加坡国家研究基金会;
关键词
Memristor arrays; Weight transfer; Overshoot suppression; Vector-matrix multiplication; Spiking neural networks;
D O I
10.1016/j.nanoen.2025.111261
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
This study presents a novel reset-dominant synaptic weight programming strategy for passive memristor crossbar arrays, enabling high-precision neuromorphic computing without external current compliance circuitry. We introduce a naturally formed Overshoot Suppression Layer (OSL) within a Pt/Al/TiOx/Al2O3/Pt device stack, which intrinsically limits overshoot current during the set process and allows for stable analog switching. Combined with a half-bias programming scheme, this structure significantly suppresses cell-to-cell interference, a critical challenge in high-density memristor arrays. To further enhance weight accuracy, we propose the InitialLow Resistance State (LRS) scheme, a reset-dominant programming method that minimizes abrupt conductance variation induced by set pulses. Using an incremental step pulse with verification algorithm (ISPVA), we successfully programmed 20 discrete conductance levels with a mean vector-matrix multiplication (VMM) error of 419.8 nA. Notably, 99 % of the weights fell within a 1.5 mu A error margin, demonstrating the high precision of our approach. System-level validation was conducted through hardware-based inference using a spiking neural network (SNN) trained on the MNIST dataset, achieving a classification accuracy of 88.85 %, only 1.7 % below the ideal software baseline. This work highlights a scalable and CMOS-compatible solution for achieving accurate, energy-efficient VMM in passive memristor arrays, offering strong potential for next-generation neuromorphic hardware.
引用
收藏
页数:13
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