Signal Integrity Optimization of PCB Layout When Using an External ESD Protection Device in Automotive SerDes Applications

被引：0

作者：

Welzer, Reiner ^{[1
]}

Sjiariel, Richard ^{[4
]}

Hardock, Andreas ^{[5
]}

Pilaski, Martin ^{[3
]}

Werner, Jens ^{[2
]}

机构：

[1] RF, Wireless, EMC Laboratory

[2] ESD, EMC

来源：

IEEE Electromagnetic Compatibility Magazine | 2024年 / 13卷 / 04期

关键词：

3D simulations; APIX; ESD; PCB Layout; SerDes; Signal Integrity;

D O I：

10.1109/MEMC.2024.10942583

中图分类号：

学科分类号：

摘要：

In this paper authors present a method to improve the signal integrity of the SerDes automotive link APIX, to meet the signal integrity requirements even when using an external ESD protection. This was achieved by reduction of parasitic capacitance underneath the ESD protection device itself and the adjacent traces. 3D simulations in frequency domain up to 8 GHz, time domain reflectometry (TDR), and S-parameter measurements were used for validation of this method. © 2012 IEEE.

引用

页码：61 / 67

页数：6

共 8 条

[1]

(2024)

[2]

Pozar D.M., Microwave Engineering, (2012)

[3]

Wendt T., Yang C., Schuster C., Hernandez J.E., Schutt J., Signal Integrity Assessment of External ESD Protection for Gbit/s Data Rates on Ceramic Test Fixture, 2022 IEEE 26th Workshop on Signal and Power Integrity (SPI), pp. 1-4, (2022)

[4]

Huang Y.-C., Et al., A Simple Method to Improve Signal Integrity of Electrotatic Discharge Protection Devices

[5]

Kinger Cai X., Wang K., Kraskoff N.E., Effectively compensating parasitic capacitance of ESD component for high-speed differential channel in high density routing platform, 2010 Asia-Pacific International Symposium on Electromagnetic Compatibility, pp. 358-361, (2010)

[6]

Hardock A., Pilaski M., Local PCB Layout Tweaks for Improved Signal Integrity When Using ESD Protection Devices, (2023)

[7]

(2024)

[8]

(2024)

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