Artificial Optoelectronic Synapse Featuring Bidirectional Post-Synaptic Current for Compact and Energy-Efficient Neural Hardware

Conventional hardware neural networks (HW-NNs) have relied on unidirectional current flow of artificial synapses, necessitating a differential pair of the synapses for weight core implementation. Here, an artificial optoelectronic synapse capable of bidirectional post-synaptic current (IPSC) is presented, eliminating the need for differential synapse pairs. This is achieved through an asymmetric metal contact structure that induces a built-in electric field for directional flow of photogenerated carriers, and a charge trapping/de-trapping layer in the gate stack (h-BN/weight control layer) that can modulate the surface potential of the semiconductor channel (WSe2) using electrical signals. This structure enables precise control over the direction and magnitude of injected charge. The device demonstrates key synaptic behaviors, such as long-term potentiation/depression and spike-timing-dependent plasticity. A fabricated 3 x 2 artificial synapse array shows that the bidirectional IPSC characteristic is compatible with multiply-accumulate operations. Finally, the feasibility of these synapses in HW-NNs is demonstrated through training and inference simulations using the MNIST handwritten digits dataset, yielding competitive recognition rates and reduced total energy consumption for updating weights of the weight core compared to unidirectional IPSC-based systems. This approach paves the way toward more compact and energy-efficient brain-inspired computing systems.