VelociTI: An Architecture-level Performance Modeling Framework for Trapped Ion Quantum Computers

Trapped-ion (TI) qubit architectures have recently become a promising candidate for designing and building quantum computers. In the current noisy-intermediate scale quantum (NISQ) era, TI qubits stand out for their connectivity and reliability over other candidates such as superconducting qubits. However, physical constraints stemming from fine-grained frequency control of TI qubits introduce limitations to the maximum number of trapped-ions in a quantum computing system. This fundamentally challenges the design of large TI-based quantum computers, with various quantum applications requiring a large number of qubits for practical realization. Recent work has proposed TI Quantum Charge Coupled Devices (QCCD) which provides mechanisms to link multiple ion-chains together to address the issue of scalability. While such advances help increase the total qubit count in a TI system, the weak links between ion chains introduce a performance bottleneck and gate-latency penalty. Prior TI modeling toolflows have not explored the performance and scalability implications introduced by weak links on the design of future TI systems; in this work, we directly elevate the weak link as an architectural knob, and present an architecture-level performance modeling framework called VelociTI. We use VelociTI to study the performance and scalability trade-offs in a trapped-ion quantum computing design and find that optimal scheduling of qubits can provide a 6.2x speedup in performance. Additionally, our analysis shows that scaling TI quantum computers horizontally (i.e., minimizing the use of weak links and maximizing the chain length) results in a 20% average speedup compared to using more chains for qubit placement.