8GHz Multi-Phase Ring VCO Design with Wide Tuning Range for SerDes Applications in 6nm FinFET Process

被引：0

作者：

Reddy, Ravuru Vasudeva ^{[1
]}

Rapina, Siva Kumar ^{[1
]}

Hazra, Siddhartha ^{[1
]}

Sarangam, K. ^{[2
]}

机构：

[1] Microchip Technol India Pvt Ltd, Mixed Signal Dev Grp, Bangalore, Karnataka, India

[2] Natl Inst Technol, Dept ECE, Warangal, Andhra Pradesh, India

来源：

2025 38TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2024 23RD INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, VLSID | 2025年

关键词：

Active Inductor; CDR; DRO; Delay cell; FinFET; Phase Noise; PLL; RO; Ring VCO; SerDes; PHASE NOISE; JITTER;

D O I：

10.1109/VLSID64188.2025.00065

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper the design of 8-phase, 8GHz pseudo Differential Ring Oscillator (DRO), in 6nm FinFET process technology with a supply voltage of 0.8V +/- 5% and temperature range of -40 degrees C to +125 degrees C, is shown. Two Basic Delay Cells (BDC-1 and BDC-2) are proposed and the performance of the DROs, using the two BDCs, are compared with architectures from the literature. The DROs, using BDC-1 and BDC-2, have wide Frequency Tuning Range (FTR) of 4GHz (from 9.5GHz to 5.5GHz) and 3.29GHz (from 9.29GHz to 6GHz) with a Phase Noise (PN) of -78.43dBc/Hz and -83.41dBc/Hz @ 1MHz offset from the carrier frequency, respectively under nominal PVT conditions. The input control Voltage Tuning Range (VTR) is approximately from 0.16V to 0.64V (i.e., 20% to 80% of the nominal supply voltage). The BDC-1 and BDC-2 based DROs have an average power of 19.5mW and 25.6mW respectively.

引用

页码：302 / 307

页数：6

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