Design Considerations of High-Frequency-Reference Fractional-N PLL: Architecture and Nonidealities

被引：0

作者：

Yang, Dihang ^{[1
]}

Murphy, David ^{[1
]}

Darabi, Hooman ^{[1
]}

Behzad, Arya ^{[1
]}

Ruby, Richard ^{[1
]}

Parker, Reed ^{[1
]}

机构：

[1] Broadcom Inc, San Jose, CA 95134 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2025年

关键词：

Phase locked loops; Noise; Harmonic analysis; Mixers; Gain; Logic gates; Frequency modulation; Power harmonic filters; Indexes; Prototypes; Charge-pump phase frequency detection; delta-sigma modulator (DSM); fractional-N phase-locked loop (PLL); frequency synthesizer; harmonic-mixing (HM) PLL; PLL noise optimization; PLL nonlinearity; sampling phase detection; subsampling phase detection; xor phase detection; PHASE-NOISE; RING OSCILLATOR; SYNTHESIZER; JITTER;

D O I：

10.1109/JSSC.2025.3548028

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents two calibration-free 7-nm phase-locked loop (PLL) prototypes with high-frequency reference (high-ref): a 240-MHz-driven conventional xor-phase-detector-based PLL and a 2285-MHz-driven harmonic-mixing (HM) PLL, achieving FoMs of -258 and -261 dB, respectively. A frequency-domain analysis of the phase detector's (PD's) linearity and gain validates the xor PD as an optimal choice for high-ref PLL architectures. In addition, a first-order pulse-position modulation (PPM) noise model, which arises in high-ref PLLs, is incorporated into Perrott's existing delta-sigma modulator (DSM) noise model, providing guidance on the choice of reference frequency in high-ref PLL architectures.

引用

页数：14

共 43 条

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