Direct Flip-Chip Bonding of SiC ICs on Alumina Substrate Using Gold Stud Bumps for up to 600 °C High-Temperature Applications

被引:0
作者
Li, Feng [1 ]
Shi, Jiaqi [1 ]
Lamsal, Buddhi Sagar [1 ]
Chen, Xiaoqing [1 ]
机构
[1] Univ Idaho, Dept Elect & Comp Engn, Moscow, ID 83844 USA
来源
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2025年 / 15卷 / 06期
基金
美国国家科学基金会;
关键词
Silicon carbide; Gold; Substrates; Flip-chip devices; Aging; Bonding; Thermal resistance; Packaging; Electrical resistance measurement; Conductors; Electronic packaging; flip-chip bonding; high temperature; integrated circuit (IC); silicon carbide (SiC);
D O I
10.1109/TCPMT.2025.3537101
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This article studies the feasibility of direct flip-chip bonding of silicon carbide (SiC) chips onto alumina substrate for high-temperature applications up to 600 degrees C. SiC dummy chips were prepared with sputtered thin-film Ti/TaSi2/Pt metal conductive pads, while alumina substrates were made with screen-printed thick-film gold conductive pads with a film thickness of about 12 mu m. Thermocompression flip-chip bonding was implemented with gold stud bumps made using a wire bonder. Two strategies were used in the flip-chip bonding and compared: bump-on-substrate (BoS), where gold stud bumps were made on the conductive pads of the alumina substrate, and bump-on-chip (BoC), where gold stud bumps were made on the thin-film conductive pads of the SiC chip. The SiC flip-chip packages showed a trend of decreasing daisy chain electric resistance after thermal aging and stabilization. Die shear tests and daisy chain electrical resistance measurements were carried out for the BoS and BoC packages before and after up to 16 days of thermal aging in lab air at 600 degrees C. Die shear tests showed that the bonding strength of the packages increased from about 15 g force per bump (gf/bump) before thermal aging to about 40 gf/bump after thermal aging because of the effects of thermal annealing.
引用
收藏
页码:1359 / 1366
页数:8
相关论文
共 16 条
[1]   Electrical and morphological characterization of platinum thin-films with various adhesion layers for high temperature applications [J].
Ababneh, A. ;
Al-Omari, A. N. ;
Dagamseh, A. M. K. ;
Tantawi, M. ;
Pauly, C. ;
Muecklich, F. ;
Feili, D. ;
Seidel, H. .
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2017, 23 (03) :703-709
[2]  
Brown WilliamD., 2006, Advanced Electronic Packaging, V2nd
[3]  
Chen LY, 2021, Additional Conferences (Device Packaging HiTEC HiTEN & CICMT), V2021, P000069, DOI [10.4071/2380-4491.2021.hitec.000069, 10.4071/2380-4491.2021.hitec.000069, DOI 10.4071/2380-4491.2021.HITEC.000069]
[4]  
Chen LY, 2019, Journal of Microelectronics and Electronic Packaging, V16, P78, DOI [10.4071/imaps.873073, 10.4071/imaps.873073, DOI 10.4071/IMAPS.873073]
[5]  
Di Cino M, 2022, Semiconductor Science and Information Devices, V4, P8, DOI [10.30564/ssid.v4i1.4474, 10.30564/ssid.v4i1.4474, DOI 10.30564/SSID.V4I1.4474]
[6]  
Elenius P., 2000, Chip Scale Review, V4
[7]  
Li F, 2024, IEEE MIRCOELECT ELEC, P1, DOI [10.1109/INFOCOMWKSHPS61880.2024.10620828, 10.1109/WMED61554.2024.10534140]
[8]   Flip-Chip Bonding for SiC Integrated Circuits With Gold Stud Bumps for High Temperature Up To 600 degree celsius Applications [J].
Li, Feng .
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2024, 14 (04) :705-713
[9]   Metal-to-Metal Flip-Chip Bonding for HighTemperature 3D SiC IC Integration and Packaging [J].
Li, Feng ;
Shi, Jiaqi .
2023 IEEE WORKSHOP ON MICROELECTRONICS AND ELECTRON DEVICES, WMED, 2023, :14-17
[10]   3-D Stacking of SiC Integrated Circuit Chips With Gold Wire Bonded Interconnects for Long-Duration High-Temperature Applications [J].
Li, Feng .
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2022, 12 (10) :1601-1608