Parallel Feedback Controlled Low-Power and Reliable Schmitt Trigger Circuit

被引：0

作者：

Khola, Raveesh ^{[1
]}

Kumar, Kaushal ^{[1
]}

Dhale, Nitesh Kumar ^{[1
]}

Kannaujiya, Aryan ^{[1
]}

Shahe, Ambika Prasad ^{[1
]}

机构：

[1] Indian Inst Technol Jammu, Elect Engn Dept, IC ResQ Lab, Jammu 181221, J&K, India

来源：

VLSI FOR EMBEDDED INTELLIGENCE, VDAT 2023 | 2024年 / 1210卷

关键词：

Schmitt Trigger; Hysteresis; Positive feedback; Noise immunity;

D O I：

10.1007/978-981-97-3756-7_5

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work highlights an optimized low-power Schmitt trigger circuit with parallel connected feedback.(PF - ST). Different Schmitt trigger configurations and their performance have been studied. All the simulation work is performed by using Cadence virtuoso 45nm CMOS technology. The proposed circuit offers significant hysteresis width that can be used where the input signal has the presence of noise. We have also analyzed dynamic and leakage power dissipation, and propagation delay considering variations in temperature and supply voltage. The optimized design offers 0.207x, 0.180x, and 1.054x of dynamic and leakage power consumption and propagation delay less than conventional ST circuits. 2000 Monte Carlo simulation shows that our PF-ST has less effect on process variations.

引用

页码：53 / 62

页数：10

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