Evaluation of the Versal Intelligent Engines for Digital Signal Processing Basic Core Units

被引:0
作者
Flores, Fernando [1 ]
Valdes Pena, Maria Dolores [2 ]
Villapun Sanchez, Jose Manuel [1 ]
Costa Pazo, Jesus Manuel [3 ]
Quintans Grana, Camilo [2 ]
机构
[1] Indra, Digital Hardware Airborne Syst Area, Vigo, Spain
[2] Univ Vigo, Dept Elect Technol, Vigo, Spain
[3] Indra, Signal Proc Naval Syst Area, Vigo, Spain
来源
2024 39TH CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS, DCIS | 2024年
关键词
Versal; AI Engine; DSP58; SoC; FIR; FFT; DSP;
D O I
10.1109/DCIS62603.2024.10769170
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, the novel Intelligent Engines of the Versal Adaptive Compute Acceleration Platform (ACAP) from AMD (formerly Xilinx) are evaluated for Digital Signal Processing (DSP) applications. Different configurations of Finite Impulse Response (FIR) filters and Fast Fourier Transforms (FFTs) serve as benchmarks. The Intelligent Engines comprise the new DSP blocks generation (DSP58) and the AI Engines (AIEs). As FIR filters and FFTs are core units in almost all DSP algorithms, this benchmark is of great value for understanding the best way to implement DSP algorithms on these new devices. A comparison of several implementations using the Programmable Logic (PL) and DSP blocks of Zynq Ultrascale+ and Versal families, along with the scalar and vector units of the Versal's AIEs, is provided. Throughput, latency, power consumption and hardware cost are measured as key performance indicators for the algorithms under test. Results highlight the Versal architectural advantages in optimizing compute-intensive applications and its potential in terms of throughput, power and resources efficiency. The outcomes also provide valuable insights into the optimal configurations for DSP algorithms, depending on the used data types, filter taps, FFT length, as well as the latency, throughput, power and resources constraints of the target application.
引用
收藏
页码:123 / 128
页数:6
相关论文
共 19 条
[1]  
Ahmad S., 2019, XILINX 1 7NM DEVICE, P1
[2]  
AMD, 2024, Versal architecture and data sheet: Overview (DS950)
[3]  
AMD, 2022, Versal ACAP DSP Engine Architecture Manual (AM004)
[4]  
AMD, 2023, Versal ACAP configurable logic block (AM005)
[5]  
AMD, 2022, Ultrascale architecture: Overview (DS890)
[6]  
AMD, 2023, Versal adaptive SOC AIE-ML (AM020)
[7]  
AMD, 2022, System-level benefits of the Versal platform (WP539)
[8]  
AMD, 2022, AI engines and their applications (WP506)
[9]  
AMD, 2020, Versal: The first adaptive compute acceleration platform (WP505)
[10]  
AMD Inc. Santa Clara CA USA, 2021, UltraScale Architecture DSP Slice (UG579)