Secrecy Rate Maximization in MIMO RIS-Aided Wireless Communications: A Hardware Accelerator Implementation for Reflection Optimization

被引:0
作者
Kompostiotis, Dimitris [1 ]
Paliouras, Vassilis [1 ]
机构
[1] Univ Patras, Elect & Comp Engn Dept, Patras, Greece
来源
2024 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, SIPS | 2024年
关键词
6G; Reconfigurable intelligent surfaces; physical layer security; MIMO; FPGA-based hardware accelerator; RECONFIGURABLE INTELLIGENT SURFACES; PHYSICAL-LAYER SECURITY;
D O I
10.1109/SIPS62058.2024.00041
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Sixth generation (6G) wireless networks envision new Internet-of-Things (IoT) applications that require faster and more secure data transmission. Reconfigurable intelligent surfaces (RISs) can improve physical-layer security in wireless communications by optimally reflecting incoming electromagnetic waves to benefit legitimate users (LUs) and simultaneously hinder eavesdroppers (ED). However, for low-latency data transmission and short-coherence-time wireless channels, optimizing the RIS configuration must be done extremely fast, thus requiring a hardware accelerator. In this paper, we consider a multi-input multiple-output (MIMO) RIS-enabled physical-layer security system and introduce a novel low-latency hardware accelerator to maximize the achievable secrecy rate by optimizing the RIS reflection coefficients. The proposed accelerator implements a Dinkelbach-based iterative algorithm, here modified for the MIMO case and to facilitate hardware implementation. Simulations reveal that high-quality solutions are obtained, compared to a theoretical upper limit. The proposed sub-1-ms latency accelerator is detailed, highlighting design choices that enable its fast operation under moderate resource requirements, and also meeting the real-time requirements of emerging 6G applications.
引用
收藏
页码:189 / 194
页数:6
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