Hybrid SORN Hardware Accelerator for Support Vector Machines

This paper presents a new approach for support vector filtering to accelerate the training process of support vector machines (SVMs). It is based on the Sets-of-Real-Numbers (SORN) number format, which provides low complex and ultra fast computing. SORNs are an interval based binary number format, showing promising results for complex arithmetic operations, e.g. multiplication or fused multiply-add. To apply SORNs to high dimensional vector arithmetic, a combination of SORN arithmetic and fixed-point adder trees is used. This Hybrid SORN approach combines the advantages of SORNs, concerning reduction of computational costs and time, and fixed point adders in terms of precision. A Hybrid SORN support vector filtering architecture is implemented on an FPGA board with Zynq 7000 XC7Z100 SoC and evaluated for the MNIST dataset. It can be considered as hardware accelerator, reducing the training time by factor 1.38 for one-versus-rest and 2.65 for oneversus-one SVM implementation.