Design of hardware accelerator for target recognition convolutional neural network based on DSP plus FPGA architecture

In response to the deployment requirements of target recognition algorithms based on convolutional neural networks (CNN) on embedded platforms, this paper proposes a hardware accelerator based on the Digital Signal Processor (DSP) + Field Programmable Gate Array (FPGA) architecture, aiming to overcome the current issues of low recognition speed and low hardware resource utilization. The system is designed based on the 6678 series DSP and the V7 series FPGA. The DSP is used as the host computer, and the design of various operators required in the CNN are completed in the FPGA as the core computing module of the accelerator. This architecture enables flexibility in implementing different neural networks by configuring different instruction sets. Within the core computing module of the FPGA, this design completes the implementation of operators such as Convolution, MaxPool, Upsample, Concat, and Split, and further focuses on optimizing the Convolution operator. For the Convolution operator, a parallel acceleration method is adopted, which improves computational speed. Moreover, a method of input reuse is adopted to minimize the number of memory accesses. Additionally, a new feature map data input cache module is designed, which reduces the occupancy of on- chip hardware resources while minimizing the time from inputting image to the start of convolution calculation, enhancing the system's real-time performance. Finally, the system is used to accelerate the You Only Look Once (YOLO) neural network. It achieves a single-frame recognition time of 135.63ms for a 640x640-sized image at 200MHZ, with a throughput of up to 100.132GOPS.