Investigation of Channel Mobility Enhancement Techniques Using Si/SiGe/GeSn Materials in Orthogonally Oriented Selective Buried Triple Gate Vertical Power MOSFET: Design and Performance Analysis

被引:0
作者
Lodhi, M. Ejaz Aslam [1 ,2 ]
Ansari, Abdul Quaiyum [2 ]
Loan, Sajad A. [3 ]
Urooj, Shabana [4 ]
Nasser, Nidal [5 ]
机构
[1] Indira Gandhi Delhi Tech Univ Women, Dept Elect & Commun Engn, Delhi 110006, India
[2] Jamia Millia Islamia, Dept Elect Engn, New Delhi 110025, India
[3] Jamia Millia Islamia, Dept Elect & Commun Engn, New Delhi 110025, India
[4] Princess Nourah bint Abdulrahman Univ, Coll Engn, Dept Elect Engn, POB 84428, Riyadh 11671, Saudi Arabia
[5] Alfaisal Univ, Coll Engn, Riyadh 11533, Saudi Arabia
关键词
triple gate; trench; selective buried; silicon-germanium; breakdown voltage; on-resistance; germanium-tin; mobility; power MOSFET; ELECTRON; SILICON; DEVICES; SOI;
D O I
10.3390/mi16040452
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
The performance of the Si MOSFET is suppressed when the channel loses its control through the gate. This paper introduces a new and novel high-channel conducting orthogonally oriented selective buried triple gate vertical power MOSFET technology to study the channel behavior compared with the conventional Si power MOSFET. Our paper investigates the performance of the proposed selective buried triple gate power MOSFET by using different channel materials (SiGe/GeSn over Si) to compare with the conventional Si MOSFET. Our 2D Silvaco simulation output significantly improves device on-current, ON-resistance, channel electron mobility, transconductance, and enhancement in various parameters governing power MOSFET. The unique design of our proposed triple gate gives very high channel mobility of 880 cm2/V<middle dot>s, which we believe to be significant in the triple gate power MOSFET domain. The results show that our optimized triple-gate device achieves an ultra-low specific ON-resistance of 0.31 m Omega<middle dot>cm(2), improving Balliga's FOM1 by 411.61% and FOM2 by 98.704%. This makes it suitable for high-speed and switching devices, compatible with various high-mobility channel materials, and well-suited for future CMOS applications.
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页数:17
相关论文
共 44 条
[1]   THE EVOLUTION OF POWER DEVICE TECHNOLOGY [J].
ADLER, MS ;
OWYANG, KW ;
BALIGA, BJ ;
KOKOSA, RA .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (11) :1570-1591
[2]   Recent advances in single crystal narrow band-gap semiconductor nanomembranes and their flexible optoelectronic device applications: Ge, GeSn, InGaAs, and 2D materials [J].
An, Shu ;
Park, HyunJung ;
Kim, Munho .
JOURNAL OF MATERIALS CHEMISTRY C, 2023, 11 (07) :2430-2448
[3]  
Baliga B.J., 2008, Fundamentals of Power Semiconductor Devices
[4]  
Calafut D.S., 2002, U.S. Patent, Patent No. [6,461,918B1, 6461918]
[5]   Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO2 Charge Trapping Layer [J].
Chen, Lun-Jyun ;
Wu, Yung-Chun ;
Chiang, Ji-Hong ;
Hung, Min-Feng ;
Chang, Chin-Wei ;
Su, Po-Wen .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2011, 10 (02) :260-265
[6]   Optimal design of triple-gate devices for high-performance and low-power applications [J].
Chiang, Meng-Hsueh ;
Lin, Jeng-Nan ;
Kim, Keunwoo ;
Chuang, Ching-Te .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (09) :2423-2428
[7]   Electron Mobility Enhancement in GeSn n-Channel MOSFETs by Tensile Strain [J].
Chuang, Yen ;
Liu, Chia-You ;
Luo, Guang-Li ;
Li, Jiun-Yun .
IEEE ELECTRON DEVICE LETTERS, 2021, 42 (01) :10-13
[8]  
Cooper James A., 2018, Materials Science Forum, V924, P680, DOI 10.4028/www.scientific.net/MSF.924.680
[9]   Fully depleted dual-gated thin-film SOI P-MOSFET's fabricated in SOI islands with an isolated buried polysilicon backgate [J].
Denton, JP ;
Neudeck, GW .
IEEE ELECTRON DEVICE LETTERS, 1996, 17 (11) :509-511
[10]   Reduced On Resistance in LDMOS Devices by Integrating Trench Gates Into Planar Technology [J].
Erlbacher, Tobias ;
Bauer, Anton J. ;
Frey, Lothar .
IEEE ELECTRON DEVICE LETTERS, 2010, 31 (05) :464-466