共 50 条
[1]
Latency Insensitive Design Styles for FPGAs
[J].
2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL),
2018,
:360-367
[3]
[Anonymous], 2022, Workcraft Website
[5]
xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification
[J].
IEEE DESIGN & TEST OF COMPUTERS,
2012, 29 (03)
:80-88
[6]
Quick Formal Modeling of Communication Fabrics to Enable Verification
[J].
2010 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT),
2010,
:42-49
[7]
Cortadella J, 2006, INT WORKSH TIM ISS S
[8]
Synchronous elastic circuits with early evaluation and token counterflow
[J].
2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2,
2007,
:416-+
[9]
Cortadella J, 2017, CONF REC ASILOMAR C, P115, DOI 10.1109/ACSSC.2017.8335149