Frame-Unit Operating Neuron Circuits for Hardware Recurrent Spiking Neural Networks

被引：0

作者：

Kim, Yeonwoo ^{[1
,2
]}

Jeon, Bosung ^{[1
,2
]}

Park, Jonghyuk ^{[1
,2
]}

Choi, Woo Young ^{[1
,2
]}

机构：

[1] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 08826, South Korea

[2] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 08826, South Korea

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2025年 / 72卷 / 04期

关键词：

Hardware; Circuits; Neurons; MOSFET; Firing; Arrays; Spiking neural networks; SPICE; Threshold voltage; Recurrent neural networks; Neuromorphic system; neuron circuit; recurrent neural network (RNN); spiking neural network (SNN); synaptic array; MEMORY;

D O I：

10.1109/TED.2025.3546185

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A frame-unit operating neuron circuit (f-NC) for hardware recurrent spiking neural networks (RSNNs) is proposed. The proposed f-NC enables the two essential features required in RSNNs, which have been challenging to implement in conventional integrate-and-fire (I&F) neuron-based systems: 1) the ability to recurrently feed the output from the previous state ( t - 1) as input to the current state ( t ) in the frame unit, and 2) the implementation of a tanh activation function. System-level simulations of the Free Spoken Digits Dataset are performed to confirm the operation of RSNNs with f-NCs with charge-trap flash (CTF)-based AND-type synaptic arrays, which store 16-state weights and operate array-and circuit-level vector-matrix multiplication (VMM). It shows 97.05% RSNN inference accuracy, including quantized synaptic weight and nonidealities in the activation function of the neuron circuit.

引用

页码：1795 / 1801

页数：7

共 30 条

[1] IMPULSE: A 65-nm Digital Compute-in-Memory Macro With Fused Weights and Membrane Potential for Spike-Based Sequential Learning Tasks [J].