Zynq-7000 FPGA-in-the-loop implementation of fractional-order PID controllers using a hybrid fixed-point and floating-point approach

被引:0
作者
Ali, Aijaz [1 ]
Bingi, Kishore [1 ]
Ibrahim, Rosdiazli [1 ]
Bansal, Lalit [2 ]
Omar, Madiah [3 ]
机构
[1] Univ Teknol PETRONAS, Dept Elect & Elect Engn, Seri Iskandar, Malaysia
[2] Cent Sci Instruments Org CSIR, Sect 30, Chandigarh 160030, India
[3] Univ Teknol PETRONAS, Dept Chem Engn, Seri Iskandar, Malaysia
来源
ENGINEERING RESEARCH EXPRESS | 2025年 / 7卷 / 02期
关键词
Zynq-7000; FPGA; fixed-point; floating-point; fractional-order controllers; Xilinx Vivado; FPGA-in-the-Loop; resource utilization;
D O I
10.1088/2631-8695/add4ca
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Implementing FPGA-based fractional-order controllers in real-time applications can be challenging due to their memory dependencies. These dependencies require high-order integers, leading to several design complications. Issues such as large design sizes, space exploration, and difficulty creating configurable hardware can affect resource utilization, power consumption, and accuracy. Therefore, this paper presents the implementation of a family of fractional-order PID controllers on the Zynq-7000 FPGA using the Tustin approximation technique, which addresses the memory dependency issue in real-time applications. A hybrid approach combining fixed and floating-point methods enhances computational efficiency, reducing resource utilization alongside greater precision and accuracy. The controllers evaluated include PID, PI-PD1, PI-PD2, PIDD, PI alpha-PD1, PI alpha-PD2, PI-PD beta 1, PI-PD beta 2, PI alpha-PD beta 1, PI alpha-PD beta 2, PI alpha D beta, and PIDD beta. These controllers are implemented on three different plants, allowing for a comparison between fractional-order and traditional controllers. The design utilizes the FPGA-in-the-Loop (FIL) feature for real-time validation and performance evaluation through MATLAB/Simulink and Xilinx Vivado. In Plant 1, the PI alpha-PD2 controller exhibits the least overshoot and the shortest rise time with power consumption from Xilinx of 0.3W. Similarly, in plant 2, all the fractional-order controllers demonstrate less overshoot and quicker settling time than the integer-order controllers with a power consumption of 0.3W. Finally, in plant 3, the fractional-order controller achieves significantly less overshoot and a much shorter rise time than traditional controllers, with power consumption ranging from 3W to 4W. Overall, the performance of Zynq-7000 FPGA-based fractional-order controllers shows improvements in step response characteristics, resource utilization, and power consumption compared to the traditional controllers.
引用
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页数:33
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