Phase engineering of high-k dielectrics for application in charge-trapping memory capacitors: a mini review

Due to the advantages in down-scaling of the cell size, high-k dielectric materials have seized significant attention and been widely implemented in charge-trapping memory (CTM) capacitors. In this review, we explore the potential of high-k films as charge trapping layers (CTL) and emphasize their key roles in improving memory device performance. In particular, the crystalline phases of high-k materials matter a lot in fast storage characteristics such as data retention, operating gate voltage and storage windows, etc. This review mainly focuses on investigating the effects of different crystalline phases of high-k materials on performance of CTM devices, and the approaches of triggering phase transformation. Finally, we summarize the recent developments of crystalline metal oxides as novel CTL materials, providing mechanistic insights of phase structure-activity relationship of high-k dielectrics toward CTM devices and provide both experimental and theoretical foundations for exploitation and optimization of non-volatile memory capacitors.