Thermal Boundary Resistance Reduction by Interfacial Nanopatterning for GaN-on-Diamond Electronics Applications

GaN high electron mobility transistors (HEMTs) on SiC substrates are the highest performing commercially available transistors for high-power, high-frequency applications. However, Joule self-heating limits the maximum areal power density, i.e., operating power is derated to ensure the lifetime of GaN-based devices. Diamond is attractive as a heat sink due to its record-high thermal conductivity combined with its high electrical resistivity. GaN-on-diamond devices have been demonstrated, bringing the diamond as close as possible to the active device area. The GaN/diamond interface, close to the channel heat source, needs to efficiently conduct high heat fluxes, but it can present a significant thermal boundary resistance (TBR). In this work, we implement nanoscale trenches between GaN and diamond to explore new strategies for reducing the effective GaN/diamond TBR (TBReff). A 3x reduction in GaN/diamond TBReff was achieved using this approach, which is consistent with the increased contact area; thermal properties were measured using nanosecond transient thermoreflectance (ns-TTR). In addition, the SiN x dielectric interlayer between the GaN and diamond increased its thermal conductivity by 2x through annealing, further reducing the TBR. This work demonstrates that the thermal resistance of heterogeneous interfaces can be optimized by nanostructured patterning and high-temperature annealing, which paves the way for enhanced thermal management in future device applications.