A 0.75μA-quiescent current, output capacitor-less LDO regulator with high power supply rejection

被引：0

作者：

Zhao, Zhengliang ^{[1
,2
]}

Lang, Lili ^{[1
]}

Bi, Dawei ^{[1
]}

Dong, Yemin ^{[1
,3
]}

机构：

[1] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Mat Integrated Circuits, Shanghai 200050, Peoples R China

[2] Univ Chinese Acad Sci, Beijing 100049, Peoples R China

[3] Univ Chinese Acad Sci, Ctr Mat Sci & Optoelect Engn, Beijing 100049, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2025年 / 22卷 / 05期

关键词：

OCL-LDO; Low power; Power supply rejection; Current can- cellation; Pole-zero tracking; LOW-DROPOUT REGULATOR; HIGH-PSR; FREQUENCY;

D O I：

10.1587/elex.22.20240740

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an output capacitor-less LDO regulator (OCL-LDO) with high PSR and ultra-low quiescent current. The circuit utilizes a local feedback amplifier based BGR and a pseudo-dynamic biased error amplifier to improve its PSR. Hereinto, the modified super source follower solves the stability problem in the local loop and further reduces the output impedance. Furthermore, the nested miller compensation based on dynamic nulling resistor (DNR-NMC) is utilized to keep stable in the full load range. The transient enhancement circuit can reduce the overshoot and outshoot voltage by 68% and 35%, respectively. This design implemented in 180nm technology occupies an area of 0.132 mu m2 and provides a controllable output over a supply range of 2.5V-5V and the maximum output current is 100mA. The PSR is less than-75dB at 100Hz and-40dB at 10kHz with the load current of 100mA. Additionally, the line regulation and load regulation are 0.08%/V and 0.21%/A, respectively.

引用

页数：6

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