In 2016, TSMC introduced the Integrated FanOut (InFO) packaging technology, which has been widely adopted in Apple's A-series processors. This packaging technology offers superior performance, high I/O density, and low energy consumption. However, reliability issues have emerged. To address these issues, our research has developed a comprehensive InFO model that includes four different types of chips, aiming to understand the inner mechanisms of warpage and stress concentration throughout the entire manufacturing and operational process. Finite Element Analysis (FEA) was conducted using ABAQUS software, combined with material models capable of accurately characterizing the thermomechanical properties of silicon chip and Epoxy Molding Compound (EMC). The study employed a multi-scale approach to establish the cross -scale models for thermomechanical simulation. The global model considered the effects of gravity, EMC backgrinding, post mold cure time and temperature, revealing their crucial roles in optimizing warpage. The first level sub-model focused on die gap, demonstrating that increasing die gap alleviates stress concentration. The second level sub -model quantitatively analyzed the impact of the mechanical constitutive model of the underfill on the reliability of microbump. The research provides theoretical guidance for enhancing the reliability of information packaging and advancing the advanced packaging technology of integrated circuits.
