A Novel Approach to Assess Board Level Solder Joint Reliability for Flip-Chip on Leadframe Package Using Finite Element Analysis

Flip Chip on Lead frame QFN has drawn significant business interests in industry because of its several advantages such as high power density, lower resistance, good thermal performance and high efficiency. Robust design is needed to qualify different reliability tests for different applications. Board level solder joint reliability (BLR) during thermal cycling is an important concern. The actual temperature cycling test is very time consuming and costly. Finite element analysis (FEA) has been a useful tool to quickly assess the solder joint fatigue life for packages like WBQFN (wire bonded quad flat non-lead), WCSPs (wafer-level chip scale) and lidded FCBGA (flip-chip ball grid array). The commonality of these packages is that each design has uniform shape of exposed leads. Lead size impact to BLR performance is not generally accounted for in typical FEA simulations, and only the most stressed pin is used for modeling correlation. However, it is not easy to implement this common modeling approach directly to flip-chip on leadframe package because of complex leadframe geometry resulting from nonuniform exposed lead size and shape. There is very little literature work from industry for BLR of flip chip on leadframe type of package.