Hardware-Efficient Polar Decoder for 5G Internet of Things Communication

被引:0
作者
Guo, Jing [1 ]
Li, Congduan [1 ]
机构
[1] Sun Yat Sen Univ, Sch Elect & Commun Engn, Shenzhen, Peoples R China
来源
IOT AS A SERVICE, IOTAAS 2023 | 2025年 / 585卷
基金
美国国家科学基金会;
关键词
Internet of things; Polar codes; Wireless communication; Hardware architecture; Field programmable gate array; SUCCESSIVE-CANCELLATION DECODER; ARCHITECTURES;
D O I
10.1007/978-3-031-70507-6_5
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Polar codes have aroused extensive attention due to their capacity-achieving property and low encoding and decoding complexity. With the increasing demand for real-time and high-quality applications, achieving low-latency communication in resource-constrained scenarios such as on Internet of Things (IoT) devices has become essential. This paper proposes a modified semi-parallel decoder for 5G IoT communication, with low decoding latency and high efficiency of hardware resources. 4-bit decoding algorithm and look-ahead approach are used in this work to reduce latency caused by conventional semi-parallel architecture. For a code length of N = 2(10), the proposed decoder improves latency by 48.64% and 75.19% than the conventional semi-parallel decoder and 2-bit decoder, separately. The significant improvement in hardware utilization rate of processing elements by 68.42% and 119.35% leads to high efficiency of hardware resources.
引用
收藏
页码:58 / 68
页数:11
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