Improving Reliability of STT-MRAM-Based Smart Material Implication

被引：0

作者：

Lanuzza, Marco ^{[1
]}

Moposita, Tatiana ^{[1
]}

机构：

[1] Univ Calabria, Dept Comp Engn Modeling Elect & Syst, Arcavacata Di Rende, Italy

来源：

2024 IEEE 24TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY, NANO 2024 | 2024年

关键词：

Smart Material Implication (SIMPLY); MTJ; STT-MRAM; Logic-in-Memory (LIM); IN-MEMORY; LOGIC;

D O I：

10.1109/NANO61778.2024.10628831

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Logic-in-Memory (LIM) architectures, particularly those based on Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM), offer a promising solution to overcome the von-Neumann bottleneck of traditional computing platforms. The smart material implication (SIMPLY) LIM scheme has been proposed to execute computations efficiently within memory units. This paper presents reliability enhanced STT-MRAM-based SIMPLY and sFALSE operations, assessing improvements in read margin (RM) and bit error rate (BER). Furthermore, the energy efficiency of the SIMPLY scheme is evaluated for the implementation of some logic operators such as NAND, XOR, and XNOR. Simulation results show that SIMPLY+ scheme results to be energy efficient, while assuring a 3.7x larger RM as compared to the conventional SIMPLY.

引用

页码：523 / 526

页数：4

共 21 条

[1] A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations [J].

Chen, Jian ;

Zhao, Wenfeng ;

Wang, Yuqi ;

Shu, Yuhao ;

Jiang, Weixiong ;

Ha, Yajun .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 30 (06) :769-780

[2] Compact Modeling of Perpendicular STT-MTJs']Js With Double Reference Layers [J].

De Rose, Raffaele ;

d'Aquino, Massimiliano ;

Finocchio, Giovanni ;

Crupi, Felice ;

Carpentieri, Mario ;

Lanuzza, Marco .

IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2019, 18 :1063-1070

[3] A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs']Js [J].

De Rose, Raffaele ;

Lanuzza, Marco ;

d'Aquino, Massimiliano ;

Carangelo, Greta ;

Finocchio, Giovanni ;

Crupi, Felice ;

Carpentieri, Mario .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (10) :4346-4353

[4] AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing [J].

Garzon, Esteban ;

Lanuzza, Marco ;

Teman, Adam ;

Yavits, Leonid .

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2023, 13 (01) :408-421

[5] Assessment of STT-MRAMs based on double-barrier MTJs']Js for cache applications by means of a device-to-system level simulation framework [J].

Garzon, Esteban ;

De Rose, Raffaele ;

Crupi, Felice ;

Trojman, Lionel ;

Finocchio, Giovanni ;

Carpentieri, Mario ;

Lanuzza, Marco .

INTEGRATION-THE VLSI JOURNAL, 2020, 71 (71) :56-69

[6] Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework [J].

Garzon, Esteban ;

De Rose, Raffaele ;

Crupi, Felice ;

Trojman, Lionel ;

Lanuzza, Marco .

MICROELECTRONIC ENGINEERING, 2019, 215

[7]

Ikeda S, 2010, NAT MATER, V9, P721, DOI [10.1038/NMAT2804, 10.1038/nmat2804]

[8] DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification [J].

Jahshan, Zuher ;

Merlin, Itay ;

Garzon, Esteban ;

Yavits, Leonid .

56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, 2023, :1453-1465

[9] Computing in Memory With Spin-Transfer Torque Magnetic RAM [J].

Jain, Shubham ;

Ranjan, Ashish ;

Roy, Kaushik ;

Raghunathan, Anand .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (03) :470-483

[10] A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory [J].

Jeloka, Supreet ;

Akesh, Naveen Bharathwaj ;

Sylvester, Dennis ;

Blaauw, David .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (04) :1009-1021

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