Modeling Row Hammer Effect in 3D Capacitor-less DRAM using Triple-Gated Silicon Nanosheet Device

被引：0

作者：

Son, Jimin ^{[1
]}

Park, Jun Young ^{[1
]}

Lee, Taeeun ^{[1
]}

Woo, Sola ^{[1
]}

Yu, Shimeng ^{[2
]}

机构：

[1] Pukyong Natl Univ, Dept Elect & Commun Engn, Busan, South Korea

[2] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA USA

来源：

2024 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, SISPAD 2024 | 2024年

基金：

新加坡国家研究基金会;

关键词：

3D stackable DRAM; row hammer effect; retention time; capacitor-less DRAM; feedback mechanism;

D O I：

10.1109/SISPAD62626.2024.10733087

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A monolithically stackable 3D capacitor-less DRAM structure using triple-gated silicon nanosheet device is demonstrated using TCAD simulation. Our proposed device exhibits a low programming voltage of 1.8 V, a high current sense margin of 78 mu A, a fast speed of 5 ns and a data retention time of more than 104 s. In addition, we evaluate the row hammer effect on the 3D array level, including program, erase, read, and hold operations. The simulation results show a robust storage node potential despite repeated attack operations from the neighboring cell.

引用

页数：4

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