A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization

被引:1
作者
Song, Hyoseok [1 ]
Kim, Kwangmin [2 ]
Kim, Gain [3 ]
Kim, Byungsub [4 ,5 ,6 ,7 ]
机构
[1] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 37673, South Korea
[2] Samsung Elect, Hwaseong Si 18448, South Korea
[3] Daegu Gyeongbuk Inst Sci & Technol, Dept Elect Engn & Comp Sci, Daegu 42988, South Korea
[4] Pohang Univ Sci & Technol, Grad Sch Semicond Technol, Dept Elect Engn, Pohang 03722, South Korea
[5] Pohang Univ Sci & Technol, Grad Sch Semicond Technol, Dept Convergence IT Engn, Pohang 03722, South Korea
[6] Pohang Univ Sci & Technol, Grad Sch Semicond Technol, Dept Semicond Engn, Pohang 03722, South Korea
[7] Yonsei Univ, Inst Convergence Res & Educ Adv Technol, Seoul 03722, South Korea
基金
新加坡国家研究基金会;
关键词
Cross-layer model; equalization; large analog/mixed-signal (AMS) circuit optimization; on-chip link; particle swarm optimization (PSO);
D O I
10.1109/TVLSI.2024.3508079
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We propose a fast algorithm to optimize on-chip equalizing link design utilizing a particle swarm optimization (PSO) method. Finding the optimal design parameters of an equalizing link requires too much computation time, because the dependency between design parameters and performances is too complex, while design space is too large. The proposed algorithm greatly reduces the optimization time by utilizing the superior efficiency of PSO in heuristic search. In experiment, on average, the proposed algorithm optimized a link design 168 x faster than the previous state-of-the-art result, requiring only 1/256 evaluation counts, and reduced computation time from about 2 h to 45 s.
引用
收藏
页码:1 / 9
页数:9
相关论文
共 13 条
[1]  
Byungsub Kim, 2009, 2009 IEEE International Solid-State Circuits Conference (ISSCC 2009), P66, DOI 10.1109/ISSCC.2009.4977310
[2]  
Chiu PW, 2017, SYMP VLSI CIRCUITS, pC56, DOI 10.23919/VLSIC.2017.8008546
[3]   An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects [J].
Choi, Minsoo ;
Sim, Jae-Yoon ;
Park, Hong-June ;
Kim, Byungsub .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62 (05) :1335-1344
[4]   A 10-mW 3.6-Gbps I/O transmitter [J].
Hatamkhani, H ;
Wong, KLJ ;
Drost, R ;
Yang, CKK .
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :97-98
[5]   Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization [J].
Jang, Ikchan ;
Lee, Yoonmyung ;
Kim, SoYoung ;
Kim, Jintae .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63 (04) :540-550
[6]   Characterization of equalized and repeated interconnects for NoC applications [J].
Kim, Byungsub ;
Stojanovic, Vladimir .
IEEE DESIGN & TEST OF COMPUTERS, 2008, 25 (05) :430-439
[7]   Equalized interconnects for on-chip networks: Modeling and optimization framework [J].
Kim, Byungsub ;
Stojanovic, Vladimir .
IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, :552-559
[8]   An Energy-Efficient Equalized Transceiver for RC-Dominant Channels [J].
Kim, Byungsub ;
Stojanovic, Vladimir .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (06) :1186-1197
[9]  
Lee S, 2015, ICCAD-IEEE ACM INT, P567, DOI 10.1109/ICCAD.2015.7372620
[10]   Particle swarm optimization (PSO). A tutorial [J].
Marini, Federico ;
Walczak, Beata .
CHEMOMETRICS AND INTELLIGENT LABORATORY SYSTEMS, 2015, 149 :153-165