An 11-bit 360-MS/s Pipelined SAR ADC With Feedback Factor Compensation Using a Dynamic Negative-C-Assisted Residue Amplifier

This paper presents an energy-efficient residue amplification for low-power high-speed pipelined SAR ADC, whose residue amplifier is assisted by a dynamic negative capacitance (NC) circuit at the virtual ground. This dynamic NC for the residue amplifier increases the feedback factor while maintaining the closed-loop signal gain, thereby relaxing the requirements of the residue amplifier such as unity-gain bandwidth and open-loop gain, which subsequently leads to a power reduction of the residue amplifier. The proposed dynamic NC addresses the issues associated with static counterparts while maintaining small gain error, increased effective bandwidth, and high energy efficiency. Fabricated in a 28-nm CMOS process, the prototype 11-bit pipelined SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 58 dB and a spurious-free dynamic range (SFDR) of 77.9 dB with Nyquist input at a sampling rate of 360-MS/s, while consuming only 3.9 mW from a 0.95 V supply. This corresponds to a Walden figure-of-merit (FoM) of 16.7 fJ/conv.-step, making this work competitive among the state-of-the-art ADCs with similar speed and resolution.