Disrupting the DRAM roadmap with capacitor-less IGZO-DRAM technology

被引:0
作者
Attilio Belmonte [1 ]
Gouri Sankar Kar [1 ]
机构
[1] imec,
来源
Nature Reviews Electrical Engineering | 2025年 / 2卷 / 4期
关键词
D O I
10.1038/s44287-025-00162-w
中图分类号
学科分类号
摘要
Traditional DRAM technology, with memory bit cells consisting of one silicon transistor and one capacitor, faces major scaling challenges. A new DRAM bit cell without a capacitor and with two thin-film transistors — each with an oxide semiconductor channel such as indium-gallium-zinc-oxide — shows promises for continuing the DRAM technology roadmap, clearing the way for high-density 3D DRAM.
引用
收藏
页码:220 / 221
页数:1
相关论文
共 50 条
[31]   Design, Simulation, and Fabrication of a New Poly-Si Based Capacitor-less 1T-DRAM Cell [J].
Chen, Yun-Ru ;
Lin, Jyi-Tsong ;
Chang, Tzu-Feng ;
Eng, Yi-Chuen ;
Lin, Po-Hsieh ;
Chen, Cheng-Hsin .
2012 28TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL), 2012, :85-88
[32]   FERROELECTRIC TECHNOLOGY MAKES NONVOLATILE CAPACITOR IN A DRAM CELL [J].
MYRAVAAGNES, R .
ELECTRONIC PRODUCTS MAGAZINE, 1995, 37 (09) :18-18
[33]   Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications [J].
Oh, Hyungrock ;
Belmonte, Attilio ;
Perumkunnil, Manu ;
Mitard, Jerome ;
Rassoul, Nouredine ;
Donadio, Gabriele Luca ;
Delhougne, Romain ;
Furnemont, Arnaud ;
Kar, Gouri Sankar ;
Dehaene, Wim .
IEEE 51ST EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2021), 2021, :275-278
[34]   Floating Body Effect in Partially Depleted Silicon Nanowire Transistors and Potential Capacitor-Less One-Transistor DRAM Applications [J].
Lee, Myeongwon ;
Moon, Taeho ;
Kim, Sangsig .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2012, 11 (02) :355-359
[35]   CAPACITOR LESS DRAM CELL DESIGN FOR HIGH PERFORMANCE EMBEDDED SYSTEM [J].
Asthana, Prateek ;
Mangesh, Sangeeta .
2014 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2014, :554-559
[36]   Metal capacitor technology for application to merged DRAM logic devices [J].
Drynan, JM ;
Kishi, S .
NEC RESEARCH & DEVELOPMENT, 1999, 40 (03) :272-276
[37]   DEPLETION TRENCH CAPACITOR TECHNOLOGY FOR MEGABIT LEVEL MOS DRAM [J].
MORIE, T ;
MINEGISHI, K ;
NAKAJIMA, S .
IEEE ELECTRON DEVICE LETTERS, 1983, 4 (11) :411-414
[38]   Array transistor design challenges in trench capacitor DRAM technology [J].
Li, YJ ;
Sim, J ;
Mandelman, J ;
McStay, K ;
Ye, QY ;
Bronner, G .
2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, :85-88
[39]   Modeling Row Hammer Effect in 3D Capacitor-less DRAM using Triple-Gated Silicon Nanosheet Device [J].
Son, Jimin ;
Park, Jun Young ;
Lee, Taeeun ;
Woo, Sola ;
Yu, Shimeng .
2024 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, SISPAD 2024, 2024,
[40]   Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM [J].
Belmonte, A. ;
Oh, H. ;
Rassoul, N. ;
Donadio, G. L. ;
Mitard, J. ;
Dekkers, H. ;
Delhougne, R. ;
Subhechha, S. ;
Chasin, A. ;
van Setten, M. J. ;
Kljucar, L. ;
Mao, M. ;
Puliyalil, H. ;
Pak, M. ;
Teugels, L. ;
Tsvetanova, D. ;
Banerjee, K. ;
Souriau, L. ;
Tokei, Z. ;
Goux, L. ;
Kar, G. S. .
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,