Speeding-Up Emerging Device Development Cycles by Generating Models via Machine-Learning directly from Electrical Measurements

被引:0
作者
Trommer, J. [1 ]
Reuter, M. [2 ]
Bhattacharjee, N. [1 ]
He, Y. [1 ,4 ]
Sessi, V [3 ]
Drescher, M. [3 ]
Zier, M. [3 ]
Simon, M. [1 ]
Ruttloff, K. [3 ]
Li, K. [3 ]
Zeun, A. [3 ]
Seidel, A-S [3 ]
Metze, C. [3 ]
Grothe, M. [3 ]
Jansen, S. [3 ]
Galderisi, G. [1 ]
Havel, V [1 ]
Slesazeck, S. [1 ]
Hoentschel, J. [3 ]
Hofmann, K. [2 ]
Mikolajick, T. [1 ,4 ]
机构
[1] NaMLab gGmbH, D-01187 Dresden, Germany
[2] Tech Univ Darmstadt, Integrated Elect Syst Lab, D-64283 Darmstadt, Germany
[3] GlobalFoundries Fab1 LCC & Co KG, Dresden, Germany
[4] Tech Univ Dresden, Chair Nanoelect, D-01187 Dresden, Germany
来源
2024 50TH IEEE EUROPEAN SOLID-STATE ELECTRONICS RESEARCH CONFERENCE, ESSERC 2024 | 2024年
关键词
Fully-Depleted-Silicon-on-Insulator (FD-SOI); Emerging Devices; Compact Modelling; Machine Learning;
D O I
10.1109/ESSERC62670.2024.10719591
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work we present how an empirical compact model can be constructed directly from current measurement data by employing a machine learning technique. We demonstrate our approach on emerging dual-gated reconfigurable device test structures, which have been fabricated directly on an industrial 22 nm process. Variability of key figures of merit in reconfigurable field effect transistor test structures in the early development stage is analysed. The resulting model enables a fast adaptation to new geometries and provides simulation speed and convergence properties of a compact model, while being also flexibly adaptable to new technological iterations, thus speeding-up development cycles.
引用
收藏
页码:217 / 220
页数:4
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