Analysis of typical high speed link based on Through Silicon Via in three-dimensional Integration System

With the continuous development of the three-dimensional integrated circuits technology, high-speed link design is particularly critical for system performance improving. The interconnect network based on TSV can realize high-speed signal transmission pathway in the encapsulation level microsystem constructed by three-dimensional integration, which is of great value for the realization of highperformance computing, high speed and large capacity Internet of Things applications. This paper studies the typical link structure modeling based on Through Silicon Via (TSV). Models of two ports, six ports and eight ports cross layer highspeed link are established and simulated. PAD, RDL, TSV, transfer layer and package layer are all taking into consideration in the models. Crosstalk between adjacent lines under GS (ground-signal) transmission mode is analyzed by comparing S parameters, eye charts, electric field performance, etc. corresponding to the number of different ports, so as to achieve low crosstalk and wiring density. The capacitive coupling parameters caused by micron-level interconnect spacing and inductive coupling parameters caused by micron-level interconnect length and line width are extracted, and the equivalent circuit model of RLGC composed of distributed parameters resistance (R), inductance (L), conductance (G) and capacitance (C) is established. The signal integrity is further verified considering the influence of crosstalk and coupling. In addition, the high-speed link structure is drawn and fabricated on the PCB board. The transmission performance is measured and compared with the simulation data to determine the feasibility of the link. This work provides different port design schemes for high-speed link signal integrity design, and provides theoretical guidance and basis for practical engineering.