VLSI Implementation of crypto coprocessor using AES and LFSR

Data security has been a major concern as that of the faster processing of data. As the capability of data processing is being evolved, the attacks on these devices for the extraction of data also have been increasing day by day. The purpose of this work is to optimise the security of current crypto coprocessors with the help of Linear Feedback Shift Register (LFSR) as key generator. The integration of LFSR with Advanced Encryption Standard (AES) will enhance the security when considering hash algorithms that have hardcoded keys which can be extracted through back tracing. By making the key input of the AES random, the device will be less prone to hardware attacks and back tracing the algorithm to extract the key value and thereby the data will be difficult. Here AES with 128-bit block size and key size is integrated with the 128-bit LFSR. All the simulations and implementations are done on Xilinx-Vivado.