An Ultra-Low Power Low- IF BLE Receiver for IoT Applications

In this paper an ultra-low power BLE receiver in 65-nm CMOS technology is presented. A low-IF structure has been chosen for the proposed receiver. The proposed receiver consists of four parts including LNTA, single to balance passive mixer, TIA and Gm-C Filter. The combination of current reuse and LC-lumped circuits in the LNA stage, the power consumption is significantly reduced. A Gm-C filter is used to decrease in image signal. By using four digital bits in LNA, the receiver is tuned in desired bandwidth. Also, four digital bits are used in TIA and Gm-C filter to control gain. Four digital bits are considered for the same attenuation of the image signal in the in-Phase and quadrature output signals. The proposed receiver has been implemented in TSMC 65-nm CMOS technology. The receiver achieves a gain of 51 dB, noise figure of 9.5 dB, IRR above 26 dB, sensitivity -90 dBm while power consumption is 250 mu W from 0.8 V supply.