Fast approximate booth multiplier for error resilient applications

Approximate computing is a computing paradigm that allows compromises in the accuracy of computations and reduces computational resources while gaining advantages in performance. This can be applied to applications like image processing, machine learning, neural networks, etc., which can tolerate errors without significantly degrading the efficiency. Here, we present the implementation and detailed analysis of approximate Modified Booth multipliers that use approximate 4 : 2 compressors for the reduction of partial products. Resource usage and delay are studied for both field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations. Accuracy is estimated using standard quality metrics. Results show that the proposed multipliers give significantly better accuracy with fewer delays while using comparable resources when contrasted with existing implementations. For 16-bit multipliers, accuracy is two orders of magnitude less than the next best implementation, with 40% less delay. Practical applicability of the proposed multiplier is demonstrated by incorporating it in discrete cosine transform (DCT) used for performing Joint Photographic Experts Group (JPEG) compression.