Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching

被引：0

作者：

Fang, Zhenghan ^{[1
]}

Naviner, Lirida ^{[2
]}

Wang, Wen ^{[1
]}

Le, Wei ^{[1
]}

Cai, Hao ^{[1
]}

机构：

[1] Southeast Univ, Natl ASIC Syst Engn Ctr, Nanjing, Peoples R China

[2] Inst Polytech Paris, Telecom Paris, LTCI, Palaiseau, France

来源：

2024 37TH SBC/SBMICRO/IEEE SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2024 | 2024年

基金：

中国国家自然科学基金;

关键词：

Spin orbit torque magnetic random access memory (SOT-MRAM); reliability issues; Behavioral modeling; advanced technology nodes; SOT-MRAM; STT-MRAM; MEMORY;

D O I：

10.1109/SBCCI62366.2024.10704006

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work reviews the development of spin orbit torque (SOT) magnetic random access memory (MRAM) with respect to reliability over the past two decades. It presents an in-depth exploration of the foundational knowledge and physical modeling of SOT devices, detailing the impact of process, voltage, and temperature (PVT) variations alongside challenges in read and write reliability. Moreover, this review further investigates and synthesizes the recent advances in reliability enhancement strategies for SOT-MRAM at the device, manufacturing, circuit, and architectural levels. The overarching aim of this review is to foster further research into the reliability of SOT-MRAM within advanced process nodes, emphasizing its potential utility as a versatile general-purpose memory.

引用

页码：140 / 144

页数：5

共 36 条

[11] Exploring a SOT-MRAM Based In-Memory Computing for Data Processing [J].

He, Zhezhi ;

Zhang, Yang ;

Angizi, Shaahin ;

Gong, Boqing ;

Fan, Deliang .

IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, 2018, 4 (04) :676-685

[12]

Huang G. Y.-C.., 2024, 15.7 A 32Mb RRAM in a 12nm FinFet technology with a 0.0249 m2 bit-cell, a 3.2GB/S read throughput, a 10Kcycle write endurance and a 10-year retention at 105C, P288

[13] Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays [J].

Hui, Yajuan ;

Li, Qingzhen ;

Liu, Cheng ;

Zhang, Deming ;

Miao, Xiangshui .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71 (04) :2309-2313

[14]

Ito T., A 20Mb embedded STT-MRAM array achieving 72

[15] A Dual-Domain Dynamic Reference Sensing for Reliable Read Operation in SOT-MRAM [J].

Kim, Jooyoon ;

Jang, Yunho ;

Kim, Taehwan ;

Park, Jongsun .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69 (05) :2049-2059

[16]

Kim T.., 2020, Dynamic-reference based early write termination for low energy SOT-MRAM, P1

[17]

Liu L., 2022, Journal of Science: Advanced Materials and Devices.

[18] STT-MRAM Sensing: A Review [J].

Na, Taehui ;

Kang, Seung H. ;

Jung, Seong-Ook .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68 (01) :12-18

[19]

Natsui M.., 2020, Dual-Port field-free SOT-MRAM achieving 90-MHz read and 60-MHz write operations under 55-nm CMOS technology and 1.2-V supply voltage, P1

[20] Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy [J].

Oboril, Fabian ;

Bishnoi, Rajendra ;

Ebrahimi, Mojtaba ;

Tahoori, Mehdi B. .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (03) :367-380

← 1 2 3 4 →