Pattern Matching for Feasible and Efficient Physical Design Verification of Cell Libraries

This study introduces a pattern-matching method to enhance the efficiency and accuracy of physical verification of cell libraries. The pattern-matching method swiftly compares layouts of all I/O units within a specific area, identifying significantly different I/O units. Utilizing random sampling or full permutation can improve the efficiency of verification of I/O cell libraries. All permutations within an 11-unit I/O unit library can produce 39,916,800 I/O units (11!), far exceeding the capacity of current IC layout software. However, the proposed algorithm generates the layout file within 1 second and significantly reduces the DRC verification time from infinite duration to 63 seconds executing 415 DRC rules. This approach effectively improves the potential to detect layer density errors in I/O libraries. While conventional processes detect layer density and DRC issues only when adjacent I/O cells are placed due to layout size and machine constraints, in this work, the proposed algorithm selectively generates multiple distinct combinations of I/O cells for verification, crucial for improving the accuracy of physical design.