Machine Learning-Guided Design of 10 nm Junctionless Gate-All-Around Metal Oxide Semiconductor Field Effect Transistors for Nanoscaled Digital Circuits

In this paper, we introduce an innovative design approach based on combined numerical simulations and machine learning (ML) analysis to investigate the design key parameters of ultra-low scale junctionless gate-all-around (JLGAA) field-effect transistor (FET) devices. To this end, precise 3D numerical models that incorporate quantum effects and ballistic transport are employed to simulate the current-voltage (I-V) characteristics of 10 nm-scale JLGAA FET devices. The influence of design parameter variations and high-k dielectric material on the subthreshold characteristics is thoroughly examined. Various ML algorithms were employed to analyze and classify the key design parameters influencing the subthreshold figures-of-merit (FoMs), the subthreshold swing (SS) factor and ION/IOFF ratio. The obtained results highlight that channel radius and channel doping design parameters are particularly important for affecting swing factor behavior. Similarly, these features also play a significant role in predicting and affecting ION/IOFF current ratio values. Additionally, machine learning is used to determine the optimal design parameters for each figure of merit (FoM) output value. In this context, the models effectively predicted both ION/IOFF current ratios and SS classification, with Naive Bayes achieving an accuracy of 90.8% for ION/IOFF and 92.6% for SS, showcasing the model's robustness in these classification tasks.