Vertical Power Delivery for High Performance Computing Systems with Buck-Derived Regulators

With traditional power delivery architectures in state-of-the-art high-power (>1 kW) high-current density systems (>1 A/mm(2)), over 30% of the system-wide power is dissipated within the power delivery system, i.e., during the delivery of power from a printed circuit board (PCB) to functional die(s). Historically, in high-power systems, efficient low-power density voltage regulators have been placed on PCB, to minimize the conversion loss and advanced low-resistance interconnect technologies have been utilized to reduce the lateral routing loss in packaging power distribution network (PPDN). While power loss is reduced linearly with lower PPDN resistance, current reduction is desired due to the quadratic dependence of power on current. To efficiently deliver current from PCB to functional die, distributed vertical power delivery (DVPD) is preferred in this work. With this approach, power is delivered horizontally at high-voltage low-current and converted to low-voltage high-current close to functional die, near points-of-load (POLs), with optimal number of compact, power-efficient distributed on/in-interposer voltage regulators (VRs). Thus, lateral distribution of VRs is promising for mitigating conduction loss in both the VRs and horizontal packaging interconnect components. To increase the conversion efficiency and current density, an advanced network of parallel-connected vertically-stacked inductors and Gallium Nitride (GaN) power devices are considered. Analytical loss models and model-guided design methodology for optimizing the PCB-to-POL loss in a DVPD system are proposed in this work. A preferred power architecture for delivering 1-kW power to a functional 500-mm(2) die is determined based on the proposed models and methodology, exhibiting system-wide efficiency of 85.6% and power density of 2 W/mm(2).